The invention relates generally to processor instruction alignment methods and devices, and more particularly to instruction alignment methods and devices for aligning variable length instructions prior to instruction decoding and execution.
Many microprocessors and other instruction execution devices employ pipeline structures used to fetch, decode, execute and commit each instruction. In addition, processors are known to employ variable length instruction sets, such as Intel(copyright) X.86 family of microprocessors. Such microprocessors may also employ native instructions such as fixed length RISC instructions to which variable length instructions are converted to accomplish the work of the complex instructions. For example, X.86 instruction lengths are in the range of one to fifteen bytes depending upon the type of instruction. In contrast, the native instruction set may include fixed length instructions, such as instructions being four bytes in length.
In addition, such systems may fetch a fixed number of bytes during a fetch, such as 32 bytes each time a fetch occurs. Accordingly, each cache line may contain 32 bytes, which may include a number of different instructions. Accordingly, with a fixed length fetch group, where the fetch addresses are cache aligned, fetches occur on cache aligned fetch program count values. For example, although a target fetch address may be address 0xc3x978004, the fetched addresses for a fixed fetch group may start, for example, on a cache aligned fetch PC 0xc3x978000 resulting in 32 bytes ending at fetch PC 0xc3x97801 f. As a result, instruction bytes corresponding to fetch PC 0xc3x978000-0xc3x978003 have to be discarded. With variable length instructions, an instruction can wrap to another cache line. All that is typically known at the time of instruction fetch, is the starting address of the first instruction. To decode one instruction per cycle, for example, the system needs to compute the length of the first instruction and provide instruction bytes for the decoder.
One solution may be to employ a single shifter that is fed with 32 contiguous bytes of instruction stream and shifting based on the instruction length. This requires control logic to know when and how many bytes of the next fetch quanta to be applied to the shifter which is a function of the current instruction length. Also, this requires additional storage for the fetched instruction bytes to provide a continuous stream of bytes to the shifter.
Consequently, there exists a need for an instruction aligner and method for a variable length instruction set providing a reduction in memory requirements to accommodate suitable instruction alignment for decoding.